1. Field of the Invention
This invention relates to a semiconductor device, specifically a semiconductor memory device appropriately applied on a semiconductor device integrally made up of a peripheral circuit and a dynamic random memory (DRAM).
2. Description of the Prior Art
In a semiconductor device in which a peripheral circuit and a dynamic random memory (DRAM) are integrally formed on a single semiconductor device, especially a COB (Capacitor On Bit line) where the capacitor of DRAM is arranged above a bit line, there is a problem of a contact resistance that makes an electrical connection between an element and a metal wiring in a peripheral circuit. Heretofore, such a kind of the semiconductor memory device, as shown in a schematic cross sectional view thereof in FIG. 18, is prepared by the steps of: forming a memory cell transistor Tm for DRAM on a memory cell region and forming a peripheral circuit transistor Ts on a peripheral circuit (logic circuit) region on a silicon substrate 101, followed by forming a bit line 115 on an interlayer insulation film 106 of the memory cell region, and forming interlayer insulation films 110, 112 on these components, and forming a capacitor 127 for charge storage, which is comprised of a lower electrode 124, a capacitor insulation film 125, and an upper electrode 126, in a recessed portion formed in the interlayer insulation film 122. Subsequently, the bit line 115 is electrically connected to the memory cell transistor Tm through a contact 112, while the capacitor 127 is electrically connected to the memory cell transistor Tm through a contact 119. Furthermore, the capacitor 127 is covered with an interlayer insulation film 128, followed by forming a metal wiring 131 on the peripheral circuit region and electrically connecting to the peripheral circuit transistor Ts through a contact 130. In this semiconductor memory device, however, the total film thickness of the interlayer insulation films that cover the bit line 115 and the capacitor 127 in the peripheral circuit region, so that the deep contact 130 extending to the peripheral circuit transistor Ts through the thick interlayer insulation films should be formed. Such a configuration of the semiconductor memory device causes the difficulty in forming an opening hole for the contact in the interlayer insulation film, resulting in a trouble in the manufacture of the contact.
In an improved semiconductor device in the prior art, on the other hand, as shown in a cross sectional diagram of FIG. 19, each of the memory cell region and the peripheral circuit region on which the memory cell transistor Tm and the peripheral circuit transistor Ts are respectively formed is constructed by forming a contact (referred to as a cell contact) 109 in the interlayer insulation film 106 below the bit line 115 and electrically connecting the cell contact 109 to each of the transistors Tm, Ts of the respective regions. In the memory cell region, furthermore, the bit line 115 is connected to the cell contact 109, while the capacitor 127 is electrically connected to the cell contact 106 through a contact (referred to as a capacitor contact) formed in the interlayer insulation film 110 above the cell contact 106. In the peripheral circuit, a metal wiring 131 on the interlayer insulation film 128 above the capacitor 127 is electrically connected to the cell contact 109 through a contact (referred to as a metal contact) 130A. According such a configuration of the improved semiconductor device in the prior art, opening holes for the metal contact 130A may be only formed through the interlayer insulation films 128, 122, 110, respectively. Comparing with the semiconductor memory device of FIG. 18, the depth of the contact hole can be reduced, so that the process for manufacturing the contact can be simplified.
However, in such an improved semiconductor device, the upper end portion of the sell contact 109 is exposed at the surface of the interlayer insulation film 106. Thus, when the bit line 115 is formed on the upper surface of the interlayer insulation film 106, the bit line 115 may be displaced from a predetermined position as a result of a photolithographic technology. Therefore, as indicated by “X” in FIG. 19, a part of the bit line 115 interferes with the cell contact 109 to make a short circuit between the bit line 115 and the cell contact 109. Specifically, not shown in the figure, the cell contact 109 is formed by subjecting the interlayer insulation film 106 to a selective etching technology just as in the case with the typical contact hole. Thus, it can be formed in the shape of a taper such that the diameter of an upper opening is larger than the diameter of a lower opening. In other words, the upper end portion of the cell contact 109 tends to become one having a larger diameter, so that a short circuit can be easily occurred between the cell contact 109 and the bit line 115. Therefore, the restriction on pitch dimensions of the bit lines 115 may be occurred, resulting in the difficulty of highly integrated semiconductor memory device in addition to the decrease in the process yield.
Furthermore, the capacitor 127 is formed like a cylinder in the recessed portion formed in the interlayer insulation film 122 that covers the bit line 115. For increasing the capacitor, there is a need to increase the facing area between the lower electrode 124 and the upper electrode 126. In this case, if the film thickness of the interlayer insulation film 122 is increased so as to increase the dimensions of the capacitor in the film thickness direction, even though the cell contact 109 is formed, the depth of the metal contact 130A in the peripheral circuit region becomes deeper. Therefore, it becomes difficult to manufacture the contact, resulting in the decrease in the process yield. In addition, if the area of the capacitor 127 in the plane direction is increased, there is a restriction on proving the memory cell corresponding to the capacitor in high density and the production of a highly integrated semiconductor memory device becomes difficult.